Hybrid Hardware-Software Architecture for Reconfigurable Real-Time Systems

Home

Sections:

Architecture

-Task Management

-Task Relocation

-Bus Scheduling

-Publications

-Downloads

Architecture

In our system, each task can be provided in both a software and a hardware configuration, which provide similar functionality at different QoS levels. A software configuration (or SW task for simplicity) is a portion of code running on a CPU with associated data. A hardware configuration (or HW task for simplicity) is a logical function that has been synthesized for execution on the reconfigurable FPGA area. HW tasks use the 1D area model: each task occupies a rectangular area on the device; one dimension (typically the vertical one) is fixed and spans the whole device, while the other dimension can vary. All tasks are periodic, although HW tasks can run at higher frequencies than SW tasks.

The figure above shows a prototype floorplan for a Virtex-4 LX200 FPGA. The device, comprised of a rectangular grid of 192 rows and 116 columns of configurable logic blocks (CLBs), is partitioned into three zones. The left and right zones are used to implement reconfigurable regions; each hardware task occupies a variable number of adjacent regions. Reconfigurable regions, and therefore tasks, are piled vertically instead of horizontally like in Figure 1 due to homogeneity constraints: different FPGA columns contain different types of reconfigurable logic. However, the CLB structure is repeated vertically every four rows. The central region hosts the rest of the system; a block diagram is provided below. Note that all I/O traffic between tasks and the rest of the system must pass through statically positioned hardware elements known as bus macros (in red in the figure).

A CPU is used to run the operating system and SW tasks. The Internal Configuration Access Port (ICAP) controller provides reconfiguration capabilities. An interrupt controller receives interrupt requests from the ICAP controller, HW tasks and I/O devices (ex: RS232, ethernet) and forwards them to the CPU. A timer module is used to generate a periodic timing signal, which is routed to each HW task and the interrupt controller and used as the base clock resolution (jiffy) by the OS. Each HW task consists of two modules: the user logic and the interface module. The user logic implements the actual task logic. The interface module provides communication and relocation service and connects the task to an on-chip system bus. The bus is divided in two segments: the CPU segment connects the CPU and all peripherals to an external RAM chip called the system RAM, used to hold OS and software configurations instructions and data. The task bus segment connects all HW tasks to an external RAM chip called the shared RAM, used to hold shared memory data. A bridge allows communication between the two segments when required, but otherwise they can operate in parallel. Compared to a single segment solution, the proposed architecture increases the memory bandwidth available to HW tasks as accesses by the CPU to the OS RAM are not propagated on the task bus segment. The bus arbitration is based on a fixed priority scheme, which can be used to provide real-time guarantees on communication delay.