While most real-time theory excludes low-level effects such as memory access from schedulability analysis, the reality is that communication delays can heavily impact the execution time of both SW and HW tasks. Our architectural design, on the contrary, is well suited to perform bus schedulability analysis. In [Pel08], we showed how the well known technique of response time analysis can be extended to bus scheduling on the task segment assuming that all HW tasks adhere to the double-buffering communication scheme. The task bus segment is scheduled according to rate monotonic (smaller period having higher priority), with the CPU having lower priority than any HW task. The double-buffering scheme hides memory access latency and let the HW task run at maximum frequency for improved QoS. Schedulability conditions are relatively easy, at the cost of a small increment in the data (state) memory of the task.

Performing an analysis on the CPU side can be even more difficult, as the effect of cache misses can be rather unpredictable. In [Pel07b], we provide upper bounds to interference on CPU cache misses assuming that profiling information on each SW task is available. Our method assumes two inputs: a function bounding the amount of traffic generated by peripherals/HW tasks on the shared bus in any time interval, and a function representing the time distribution of cache misses in a given task trace. Our analysis then treats the bus as a switch multiplexing access to the RAM, and is able to compute a bound on the increase of computation time for the task due to bus contention. We proved that such bound is tight and can be computed in time quadratic in the number of cache misses, although usually the complexity is much smaller in practice.