Hybrid Hardware-Software Architecture for Reconfigurable Real-Time Systems

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Relocatable Task Demo for Xilinx ML401 board

This demo runs a test case similar to the one described in [Pel08]. It has been adapted to be easy to synthesize and to produce human-checkable output. You can dowload all code here.

A DES cipher task and a DES decipher task are run simultaneously. The cipher task reads input plain-text blocks from a circular buffer and produce cipher-text blocks that are then passed to the decipher. The decipher then converts the block back to their plain-text representation and prints the deciphered values on screen. The cipher can be migrated from SW to HW and vice versa at run-time. The decipher can only be executed in software but comes in two configurations with different frequencies, which are automatically adapted based on the current cipher configuration.

The DES hardware task is provided in pcores/opb_interface_v1_01_a/hdl/vhdl. The OS is provide in microblaze_0/libsrc/xilkernel_v3_00_a. Software tasks are provided in DES/src (DES cipher software configuration) and decipherOS/src (decipher task and OS initialization). To build the demo:

Compile/synthesize using Xilinx ISE 9.1 and EDK 9.1 (tested under Windows). Note: when compiling the software part of the project, make sure to not overwrite the OS files! Precompiled bitstream and .elf files are available if you do not wish to compile.
Download bitstream to Xilinx ML401 board using impact (Device Configuration->Download Bitstream from Platform Studio).
Download the two .elf files to the board SRAM. Using XMD (Debug->Launch XMD from Platform Studio): download the DES sw task by typing "dow DES/executable.elf". Then download the decipher/OS by typing "dow decipherOS/executable.elf".
Run the program (type "run" from XMD). Instructions will be provided on-screen.

Additional notes:

To allow compilation using standard EDK tool, the architecture of this demo has been slightly simplified. In particular, the hw configuration of the DES task has been pre-placed on the FPGA (compiling the partial bitstreams require access to the experimental Xilinx Partial Reconfiguration Tools). However, the full relocation logic is implemented in the OS.
To produce human checkable results, the DES cipher processes only 4 macroblocks (equivalent to 32 integers) each period instead of the maximum of 1469 specified in the paper. The HW configuration is parameterized with the macroblock number and can be quickly adjusted if a different number of macroblocks is desired. The same VHDL description has been used for the throughput experiments described in the paper.

Coming soon...

Virtex-5 implementation.
ISE 9.2 support.
Design flow tool support.