Hybrid Hardware-Software Architecture for Reconfigurable Real-Time Systems

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Modern SoC devices enable the development of hybrid embedded systems where sofware tasks, running on a traditional CPU, can coexist with hardware tasks running on reconfigurable hardware (FPGA). Compared to classic mono or multi-processor platforms, hardware execution of real-time tasks has two main advantages: 1) it can greatly increase performance and therefore system-wide QoS; 2) it enforces superior temporal isolation and predictability. At the same time, software execution is desirable for several reasons. First, it enables reuse of legacy software libraries and tasks. Second, some types of real-time tasks are unsuited to hardware implementation either because their hardware speedup is low or because they consume a low amount of system resources even when executed in software.

The main goal of this research is to develop a SoC real-time computing architecture that integrates hardware and software execution in a transparent manner, and can support QoS adaptation by means of partial reconfiguration of modern FPGA devices. In particular, our system supports the following essential features:

Task Management for QoS Adaptation:
Our design is for an open real-time embedded system where computational demand changes based on the environment and mission objectives. Tasks can be dynamically activated and terminated. Based on system-wide QoS requirements, our Task Management system allocates tasks on either the CPU or the reconfigurable area of the FPGA. Our design satisfies all real-time schedulability constraints and minimizes release jitter.
Task Relocation with Communication Transparency:
To better cope with dynamic system requirements, our architecture supports task relocation: tasks can seaminglessy migrate from software to hardware and viceversa while preserving all internal state. A specific memory layout is enforced to reduce relocation overhead and enable communication transparency: tasks can use the same set of communication primitives in both hardware and software.
Bus Scheduling with Real-Time Guarantees:
Real-time schedulability analysis relies on the knowledge of worst-case task execution times, which are highly dependent on I/O delays. As such, we provide extensive analysis of bus scheduling to derive bounds on communication latency for both hardware and software tasks.

Funding

This research was supported by the National Science Foundation through grant CNS-0237884 and grant CCF-0325716.