Marco Caccamo Associate Professor  Department of Computer Science University of Illinois Office: 4118 SC Siebel Center for Computer Science  201 N. Goodwin Avenue  Urbana, IL 61801  Phone: 217-244-0528 Fax:   217-244-6500           mcaccamo "at" illinois.edu

Marco Caccamo graduated (summa cum laude) in Computer Engineering at University of Pisa on July 1997. He received a Ph.D. in Computer Engineering from Scuola Superiore Sant'Anna (SSSUP) in January 2002. He is one of the Principal Investigators at the "Real Time System Laboratory" at UIUC. His research interests include real-time operating systems, real-time scheduling and resource management, wireless real-time networks, and quality of service control in next generation digital infrastructures.

Teaching:

• CS424  (Real-Time Systems)
• CS598mc (Special topics: Cyber-Physical Systems)
• CS431  (Embedded Systems Architecture and Software)
• CS241 (Systems Programming)
  

Research Projects:

• Hybrid hardware-software architecture for reconfigurable real-time systems: modern SoC devices enable the development of hybrid embedded systems where sofware tasks, running on a traditional CPU, can coexist with hardware tasks running on reconfigurable hardware (FPGA). The main goal of this research is to develop a SoC real-time computing architecture that integrates hardware and software execution in a transparent manner, and can support QoS adaptation by means of partial reconfiguration of modern FPGA devices.

• CSR: Memory-Centric Real-Time Scheduling for Multicore Embedded Systems. M. Caccamo (PI), Co-PI: L. Sha, National Science Foundation, CNS-1219064
• In modern automotive and avionics applications, the use of multiple sensors and especially real-time imaging sensors creates unprecedented workloads. From a computational perspective, multicore architectures have become mainstream; however, as a multicore chip is expected to process increasing volumes of data in real-time, the memory hierarchy becomes the bottleneck resource. In the worst case, task execution times can grow linearly with the number of cores in the system. This research aims at laying foundations for a modern memory-centric real-time scheduling theory that can effectively co-schedule the use of the memory hierarchy, the cores, and the on-chip network, including the I/O channels. According to the vision of Memory-Centric Scheduling, when the memory hierarchy is the system bottleneck, memory accesses should be scheduled to achieve high memory utilization. Performance of a real-time multicore system should be measured in terms of schedulable memory utilization rather than just core utilization. Ideally, the real-time constraints should be met as long as total memory utilization of all real-time applications (across all the cores contending for shared memory) is below 100%. See the presentation titled "Predictable Integration of Safety-Critical Software on COTS-based Embedded Systems" (pptx) for learning about major findings of this research.
  

• CPS: The Ectokernel Approach: A Composition Paradigm for Building Evolvable Safety-critical Systems from Unsafe Components. T. Abdelzaher (PI), Co-PIs: M. Caccamo, L. Sha, National Science Foundation, CNS-1035736
  

Former Research Projects

Awards:

• Best Student Paper Award (RTAS 2013)
• Ranked as excellent teacher by students of CS598MC (Spring 2012)
  
• IEEE Tech. Committee on RT Systems Service Award (for serving as General Chair of CPSWeek 2011)
• Best Paper Award (RTCSA 2008)
• Ranked as excellent teacher by students of CS598MC (Fall 2007)
• Best Student Paper Award (RTSS 2004)
• NSF CAREER Award (2003)

Professional Activities:

• General Chair of Cyber Physical Systems Week (CPSWeek) 2011,
  
• General Chair of IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS’11),
• Program Chair of IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS’10),
  
• Chair of WiP session at ECRTS’08 conference.
  

Publications



accesses since June 2005


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